Conventionally, polysilicon or aluminum has been widely used for forming interconnections in a semiconductor integrated circuit but now there is the need for materials having further reduced resistance, which can replace such polysilicon or aluminum materials in order to accomplish high performance and micropatterns necessary for high-speed data transmission in semiconductor integrated circuits.
For this purpose, forming metal lines of the semiconductor integrated circuit by using copper instead of aluminum used in the past has been attempted. However, patterning by dry etching as employed when forming the conventional aluminum connection is difficult with copper and also the corrosion resistance of copper is inferior. So as a process for fabricating semiconductor integrated circuit comprising metal lines inside and on the surface of the inter-layer film and contacts connecting these metal lines, both of which are made of copper, a process called dual damascene process has now been developed.
In the conventional process of fabricating semiconductor integrated circuit according to dual damascene technique based on the via-first approach, via holes are first formed through the upper SiO2 inter-layer film to the stopper film at the position where metal line is located below. Thereafter, the via holes are filled with a via-filling material such as an organic film and trenches of a certain width are formed in a depth which does not reach the stopper film.
As the organic film, ARC (Anti Reflective Coating), specifically a composition obtained by adding poly(vinyl phenol) or poly(methyl methacrylate) to a base resin comprising polyimide and novolak is used (see for example, JP-A-2001-203207).
Also, as the via-filling material deposited in the via hole, photoresist materials, melamine derivatives, guanamine derivatives, glycoluril derivatives, urea derivatives and succinyl amide derivatives are used (see for example, JP-A-2000-195955).
In the conventional dual damascene process, the organic materials mentioned above are used as the via-filling material filling the via holes. However, when plasma etching the upper inter-layer film and the via-filling material in order to form a trench, via-filling material 307 protrudes from upper inter-layer film 302 within trench 310 as shown in FIG. 3, because the etching rate of the via-filling material is lower than the etching rate of the upper inter-layer film.
Furthermore, when C4F8 is used as an etching gas, fluorocarbon deposition is easily generated from the decomposition in plasma or reaction products. Such deposition often sticks to the protruding via-filling material and prevents downward plasma etching because the deposition serves as a mask. Accordingly, when the via-filling material in the via hole is removed after completing the simultaneous etching of the upper inter-layer film and via-filling material, a deposit 308 which is chemically stable and hard to decompose remains in the opening part of via hole 306 as shown in FIG. 4.
When a deposit remains in the opening of via hole, metal lines in the upper layer cannot be formed well, leading to the problem of disconnection in the fabricated semiconductor integrated circuit.